Team & hiring
Building Tenura in the open.
A small team designing the firmware and runtime layer for disaggregated infrastructure. Right now the team is short — that's where you come in.
Today
Where we are.
We're early. Tenura is in private beta with a small set of design partners. The reference implementation is source-available, the wire spec is open, and the system is built one decision at a time — capability tokens, lease lifecycle, hardware fences, audit chain. We're honest about timelines: hardware is the slow path, and we don't pretend otherwise.
Background spans e-commerce, mobile and embedded databases, aerospace embedded systems, and security — including M&A cloud audits in HIPAA and PCI environments. The common thread: software that has to keep running while people depend on it.
Join us
We're looking for founding engineers.
The work spans the stack — Rust runtime, bare-metal firmware, silicon validation, and the protocols that let them all talk to each other. The hardest problems live at the boundaries between layers.
We're especially interested in people with deep experience in any of these areas, and the strongest engineers we've worked with have several:
Distributed systems at scale
You've built control planes, schedulers, replicated state, or multi-tenant infrastructure that real workloads run on. You argue consistency tradeoffs from experience, not papers. You've debugged a real partition, watched a tail-latency graph at 3 AM, and known which knob to turn.
Firmware & silicon bringup
You've shipped code that runs without an OS — Rust no_std or C — and
you've made existing silicon do what its datasheet promises. PCIe, MMIO, DMA,
kernel modules, register-poking, mmiotrace when the public docs run
thin. FPGA or board-bringup experience welcome.
Realtime & low-latency
You think in worst-case, not averages. RTOS work, deterministic teardown windows, jitter-sensitive control loops, telco/trading-style systems where p99 and reset time matter more than throughput. You've made a system meet a deadline, not just finish a task.
High-speed interconnect & data plane
You've worked on InfiniBand, RoCE, CXL, NVMe-oF, or similar. Stuck queue pairs, PCIe negotiation problems, fabric re-ordering bugs, queue-depth tuning — familiar territory. Below layer 4 is where the interesting failures live.
How we work
What working here is like.
- Open spec, source-available implementation. What we're building is published, discussable, and reviewable. There's no "secret sauce" we hide behind closed doors.
- Hardware is the slow path. We don't pretend silicon ships in software timeframes. Estimates are honest, even when that's annoying for a planning conversation.
- Fail closed, not best-effort. Cleanup that "usually happens" isn't cleanup. The same standard applies to how we work — we'd rather block a release than ship a thing that drifts.
- Small, async, distributed. No commute mandate. Timezone overlap matters more than co-location, and we expect everyone to write things down.
Get in touch
Tell us what you've built.
We don't need a resume — though we'll read one. We're more interested in the systems you've shipped, the bugs you found at 3 AM, and the things you're proud of that nobody asked for.
Email jobs@tenura.systems with a short note about what you've worked on
and the kind of problem you'd want to solve here. That's enough to start a
conversation.